1. Field of the Invention
The present invention relates to a semiconductor memory device. More particularly, this invention relates to a static RAM (SRAM) in which bit lines and data lines, sharing common bit lines, (pairs of common data lines) are precharged to a predetermined voltage level.
2. Description of the Related Art
In the conventional SRAM, data read from a memory cell is transferred to a sense amplifier via a pair of bit lines and a pair of common data lines. The data is then amplified by the sense amplifier. The sense amplifier operates most efficiently when the voltage level of the data read from the memory cell is at a voltage level intermediate to that of the power source. To facilitate this, conventional SRAMs incorporate circuitry to shift the voltage level of the data read from the memory cells to an intermediate level. A level shifter suitable for such a sense amplifier is proposed in Japanese Unexamined Patent Publication No. Hei 1-192078. This level shifter is illustrated in FIG. 1.
A memory cell array 101 shown in FIG. 1 has plural pairs of word lines WL0 and plural pairs of bit lines. FIG. 1 shows only one pair of bit lines BL0 and /BL0. A memory cell C0 is connected between each word line and an associated pair of bit lines. Each cell C0 comprises cell transistors T41 and T42 and gate transistors T43 and T44, with resistors R11 and R12 as their loads, The resistor R11 and the transistor T41 are connected in series, and the resistor R12 and the transistor T42 are connected in series, the former series circuit being connected in parallel to the latter one between a power source V.sub.DD and ground V.sub.SS. When any one of the word lines and an associated pair of bit lines are selected, the cell connected to the selected word line and pair of bit lines is selected. Data in that cell is then read onto the pair of bit lines.
Connected to each pair of bit lines BL0 and /BL0 is a bit equalizer 102 for precharging that pair of bit lines. The equalizer 102 utlizies PMOS transistor T45, T46 and T47.
A pair of common data lines LD0 and /LD0 are respectively connected to each pair of bit lines BL0 and /BL0 via column switches 103 and 104. The switch 103 comprises a PMOS transistor T48 and an NMOS transistor T49, and the switch 104 comprises a PMOS transistor T50 and an NMOS transistor T51. A signal which is a column selection signal CD inverted by an inverter 105 is input to the gates of the transistors T48 and T50, and the column selection signal CD is input to the gates of the transistors T49 and T51. When the column selection signal CD goes high, the switches 103 and 104 are turned on, causing the pair of bit lines BL0 and /BL0 to communicate with the pair of common data lines LD0 and /LD0 respectively.
A common equalizer 106 is connected to the pair of common data lines LD0 and /LD0 to precharge those common data lines. The equalizer 106 comprises PMOS transistors T52, T53 and T54.
A sense amplifier 108 is connected via a level shifter 107 to the pair of common data lines LD0 and /LD0. The level shifter 107 comprises NMOS transistors T55 to T59 and PMOS transistors T60 and T61. The transistors T55 and T56 have their drains connected to the power source V.sub.DD, and their gates respectively connected to the common data lines LD0 and /LD0. The sources of the transistors T55 and T56 are connected to the drains of the transistors T57 and T58. The gates of the transistors T57 and T58 are connected to the drain of the transistor T57, thus constituting a current mirror circuit. The sources of the transistors T60 and T61 are connected to the power source V.sub.DD. The transistors T60 and T61 have their drains respectively connected to the drains of the transistors T57 and T58 and their gates respectively connected to the drains of the transistors T58 and T57. The sources of the transistors T57 and T58 are connected to the ground V.sub.SS via the transistor T59. This transistor T59 is activated when the common data lines LD0 and /LD0 are selected.
The sense amplifier 108 is connected to a node N1 between the transistors T55 and T57 via a signal line LS0 and to a node N2 between the transistors T56 and T58 via a signal line/LS0. The sense amplifier 108 is constituted of a differential amplifier which amplifies the differential voltage between the signal lines LS0 and /LS0 and outputs the amplified data.
In the thus constituted SRAM, an activate signal .phi.0 is set to an L level before data is read out. Consequently, the individual transistors T45 to T47 are turned on, and the pair of bit lines BL0 and /BL0 are precharged by the power source V.sub.DD. Further, the individual transistors T52 to T54 are turned on, and the pair of data lines LD0 and /LD0 are precharged by the power source V.sub.DD.
When the activate signal .phi.0 goes high in response to a change made in an address signal, the transistors T45 to T47 and T52 to T54 are turned off, terminating the precharging of bit lines BL0 and /BL0 and data lines LD0 and /LD0.
When the column selection signal CD goes high, the column switches 103 and 104 are turned on, connecting the pair of bit lines BL0 and /BL0 to the pair of data lines LD0 and /LD0. This allows word line WL0 together with the corresponding word and bits lines to be selected. When data in the cell C0 is "1" at this time, the transistor T41 is turned off and the transistor T42 is turned on. This causes both a high level signal to be read onto the bit line BL0 and low level signal to be read onto the bit line /BL0. These signals are transferred to the level shifter 107 via the pair of data lines LD0 and /LD0. As a result, the conductance of the transistor T55 becomes small while the conductance of the transistor T56 becomes large. Consequently, the voltage level of the signal line LS0 becomes slightly higher than V.sub.DD /2 while the voltage level of the signal line/LS0 becomes slightly lower than V.sub.DD /2, as shown in FIG. 7. The levels of the signal lines LS0 and /LS0 are amplified by the sense amplifier 108 and read data DR is output.
The level shifter 107 in the SRAM shifts the voltage levels of the signals which travel through the pair of data lines LD0 and /LD0 and outputs the resultant signals to the sense amplifier 108. To accurately read data from the cell C0, therefore, it is necessary to precharge the pair of bit lines BL0 and /BL0 and pair of data lines LD0 and /LD0.
Due to the recent improvement on the reading speed of SRAMs, the precharging time for the pair of bit lines BL0 and /BL0 and pair of data lines LD0 and /LD0 has become shorter. To shorten the precharging time, it is necessary to increase the current values of the precharging elements (the transistors T45 to T47 of the equalizer 102 and the transistors T52 to T54 of the equalizer 106), or increase the current value of the data transfer elements (the transistors T55 and T56 of the level shifter 107). This requires that the area of those elements occupying on the semiconductor substrate be increased.
With the recent high integration of SRAMs, however, there is a limit to the area available with which to form the precharging elements or the data transfer elements. It is therefore as yet, remained a challenge to precharge the associated pair of nodes of the level shifter and a pair of bit lines completely to the same voltage level. Moreover, it takes time to accomplish such precharging. With larger precharged areas, the precharge takes longer, and this also interferes with the improvement on the reading speed.